The present invention relates to an apparatus for converting an analog signal to a binary digital signal.
In a facsimile system or a pattern recognition system, image information of a document sheet is converted to an analog video signal by a document read unit which utilizes a photo-electric conversion device such as a CCD (charge coupled device) line sensor, and the analog video signal is compared with a predetermined reference signal to produce a binary digital signal, which is then processed for transmission over a transmission line. Because of variations of document illumination, light intensity around the periphery of an optical lens and sensitivities of photosensitive elements corresponding to picture cells of the CCD line sensor, an analog video signal produced by the CCD line sensor in the document sheet read unit includes a distortion or "shading" which results in local reduction of the output level. In addition, because of a reduction of the light intensity of a document sheet illumination light source by aging or a change of the background of the document sheet, the absolute value of the amplitude of the analog video signal varies. Thus, when such an analog video signal is compared with the reference signal of a predetermined level to convert it to a binary digital video signal, The digital video signal which represents the image information of the document sheet may not be accurately produced. A signal binary-digitizing processing apparatus which controls the reference signal to compensate for the above-mentioned distortion or the variation of the absolute value has been proposed. For example, reference is to be made to U.S. patent application Ser. No. 151982 filed on May 21, 1980 (corresponding to Japanese Patent Application Laid-Open No. 156475/80 laid-open on Dec. 5, 1980) and U.S. Patent Application Serial No. 260090 filed on May 4, 1981 (corresponding to Japanese Patent Application Laid-Open No. 157575/81 laid-open on Dec. 4, 1981, now U.S. Pat. No. 4,420,742issued Dec. 13, 1983.
However, such apparatus may not correctly produce a binary digital signal from an analog video signal derived from the document sheet when the document sheet includes (a) a fine or thin pattern, (b) a pattern having repetitive white and black areas at a small interval and/or (c) a pattern having at least one white area in a black area.
FIG. 1 shows an apparatus similar to that shown in FIG. 1 of the copending U.S. patent application Ser. No. 260090 mentioned above. This apparatus is therefore a subject matter of the patent application which had not been publicly known before the priority date of the present application but filed prior to the priority date.
Referring to FIG. 1, a document sheet 10 driven in a direction of an arrow by drive means (not shown) is illuminated by a lamp 11 and a scanning line area extending widthwise of the document (normal to the direction of drive) is imaged on a photo-sensitive plane of a photo-electric converter array 13 through a lens 12. The photo-electric converter array 13 may be a CCD line sensor which may comprise 2048 picture cells. Voltage signals produced in the respective picture cells of the photo-electric array 13 are taken out serially in the order of its cell arrangement and applied to an analog video input terminal 1 as an analog video signal A. Such an analog video signal A usually includes 20-40% shading. Numeral 2 denotes a peak hold circuit which holds a peak value of the analog video signal A applied to the video input terminal 1 and produces an analog peak voltage B. An analog-to-digital converter 3 in a converter circuit 14 receives the analog video signal A for a scan of a white area (at the top portion of the document sheet) and the analog peak voltage B, and produces a digital coded shading profile signal C which is normalized by the analog peak voltage B and supplies the signal C to a memory 4, which stores the normalized shading profile signal C. This signal C corresponds to the above-mentioned "shading" distortion. The normalization is carried out by scaling the voltage of the analog video signal A using the peak voltage B as a reference. Any unit and any scale may be selected. The peak hold circuit 2 produces an instantaneous peak voltage Vp which follows a change in the background of the document sheet. When image information is to be processed, a digital-to-analog converter 5 in the converter circuit 14 receives the normalized shading profile signal C which is read out of the memory 4 and a current value of the analog peak voltage B produced by the peak hold circuit 2 and produces a background voltage D corresponding to white or plain background at that time. By appropriately dividing the background voltage D by a voltage dividing resistor 6, a shading-compensated reference signal E.sub.1 is produced. Numeral 7 denotes a comparing circuit which compares the analog video signal A carrying the image information with the reference signal E.sub.1 to produce a binary information signal E.sub.1 at an output terminal 8. The operations of the photo-electric converter array 13, the peak hold circuit 2 (of a digital type), the memory 4 and the converter 14 including the analog-to-digital converter 3 and the digital-to-analog converter 5 are controlled by timing signals such as a sync signal, a clock signal and/or a reset signal supplied from a control circuit 88. The control circuit 88 may include a clock generator, a sync signal generator and a counter for dividing the frequency of the output of the clock generator to define the repetition frequency of a clock signal to be used. Thus, the controller 88 supplies the sync signal and the clock signal to the array 13 for its operation, the clock signal and a reset signal to the peak hold circuit for its operation, the clock signal to the converters 3 and 5 for their operations and the clock signal to the memory 4 for determining addresses in the memory 4. If the peak hold circuit 2 is of an analog type no timing signal will be necessary.
Referring to the time chart of FIG. 2, the operation of the circuit will now be explained.
The analog information signal A which is produced by repetitively and photo-electrically scanning the document sheet includes background information scan signal trains A-1 and A-2 and pattern information scan signal trains A-3, . . . The background information scan signal train A-1 is applied to the peak hold circuit 2 which holds a peak value thereof and produces a peak hold voltage B at the output. The next incoming background information scan signal train A-2 is normalized by the peak hold voltage B for each picture cell and digitized to produce a shading profile signal C for all picture elements of a scanning line. The normalized digitization may be carried out by digitizing the background information scan signal train A-2 for all the picture elements while putting the peak hold voltage to the most significant digit MSB (a maximum value in digital representation) and a zero volt signal to the least significant digit LSB (a minimum value in digital representation). Alternately, the digitization may be carried out by dividing the background information scan signal train A-2 by the time axis and sampling the divided signals independently, or by sequentially comparing the current picture cell value with the previous picture cell value. The digital signals C are sequentially stored in corresponding addresses of the memory 4. In this manner, the normalized digitization and the storage (storage of the shading profile) of the background information scan signal train (e.g. plain background of the document sheet) are completed.
After the shading profile has been stored, the signal processing system proceeds to the process of converting the analog scan signal train to a binary-level signal. This takes place in response to the detection of a predetermined time after the initiation of the photo-electric conversion of the document sheet or to detection of a predetermined number of scanning lines. In the binary-level conversion operation, the analog scan signal train A-3 carrying the image information is applied to the information input terminal 1. In synchronism therewith, the shading profile digital signals stored at the addresses corresponding to the picture cell positions in the memory 4 are read out and applied to the digital-to-analog converter 5. The digital-to-analog converter 5 also receives the peak-hold voltage B and produces the background voltage D having the possible maximum value at the peak-hold voltage B. By constructing the peak hold circuit 2 such that it always holds a peak value of the current analog scan signal train A, it is possible to produce the background voltage D adapted to the analog scan signal train A-3 even when the plain background of the document sheet varies. The background voltage D thus produced is applied to the voltage dividing resistor 6 which produces a compensated reference voltage E.sub.1, which in turn is compared with the analog scan signal train A-3 to produce a binary information signal F.sub.1.
However, when information as represented by an analog video signal shown in FIG. 3 is included in the pattern or the image information of the document sheet 10, the image information corresponding to signal portions P.sub.1, P.sub.2 and P.sub.3, that is, a fine or thin line pattern, a white and black repetitive pattern and a white area in a black area is neglected or not correctly converted to a binary digital signal even if the compensated reference signal E.sub.1 is used.